There are a variety of semiconductor device types, one particular semiconductor device being a semiconductor memory device, such as random access memory (RAM) device. Known types of RAM devices include static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices. A DRAM device contains an array of individual memory cells. Each cell includes an integrated circuit on a substrate and conductive material for electrically connecting the cell to other structures of a memory circuit.
With reference to FIG. 1, one conventional method for depositing conductive material for backend metallization, is a single Damascene method. FIG. 1 shows a simplified single Damascene method for forming a metallization connection to a substrate. It includes depositing a non-conductive layer of material 20, e.g. borophosphosilicate glass (BPSG), on a substrate 24 and pattern etching an opening within the material 20. A conductor, e.g. a metal or a doped polysilicon, is deposited over the material 20, thereby filling in the opening and providing a covering layer on the material 20. Chemical-mechanical polishing of the conductor removes the layer of conductor on the material 20, leaving a conductive plug M1. The conductive plug M1 is positioned on a doped region 22 provided in the substrate 24. An additional layer of non-conducting material 20, e.g. BPSG, is then deposited over the conductive plug M1 and the previously deposited material 20. A via 21 is then etched in the material 20 above the conductive plug M1. A conductive barrier material 12 is then deposited within the via 21 and over the additional material 20. Then another conductive layer 16 is deposited over the barrier layer 12, thereby completing an electrical connection between conductive layer 16 and doped region 20.
Vias 21 may be formed with a positive overlap (the conductive plug M1 is of a greater diameter than the via 21), a zero overlap (the conductive plug M1 and the via 21 are the same diameter), or a negative overlap (the conductive plug M1 has a smaller diameter than the via 21). In FIG. 1, a negative overlap is shown. Because of the decreasing sizes of semiconductor devices, zero overlaps and negative overlaps are becoming more prevalent.
The conductive layers 12, 16 may be formed of any suitable conductive material, such as aluminum, copper or a highly doped polysilicon. The material 20 is preferably formed of a non-conductive material which is relatively easily removed in a chemical-mechanical polishing or etching process. Most preferably, and as noted, the material 20 is a doped silicate glass, such as, for example, BPSG.
In addition to the single Damascene method described above, a double Damascene method may be used to form a conductive connection. A double Damascene method for forming trench capacitors is described in “Dual-Damascene Challenges Dielectric Etch,” Semiconductor International, p. 68–72, August 1999.
One disadvantage associated with the above-described fabrication method is that sometimes the etched via 21 in the material 20 is offset slightly relative to the plug M1, as shown in FIG. 2. This most usually occurs in zero overlap and/or negative overlap fabrication processes. The etching of such an offset via 21 creates an offset opening portion 25 along the side of the conductive plug M1, which during the subsequent layering of the conductive layers 12, 16 may form an air gap 26 (FIG. 2). Initially, the air gap 26 is relatively small, but as the conductive layers are deposited at elevated temperatures, the gas trapped in the gap 26 expands. The presence of a sizable and expanding air gap 26 sometimes prevents deposition of, or causes a rupture in, a continuous conductive layer 12 within the opening 25, which in turn may cause a defect in the conductive connection 14. This is because the conductive layer 12 is typically formed by first depositing a seeding layer for subsequent conductor formation. When part of the seeding layer is missing, a void is formed in both the seeding layer and the conductor which is formed above it. Further, the lack of a continuous conductive layer 12 may create a higher resistance in the ultimately formed conductive connection 14.
One approach at alleviating this disadvantage is to utilize a different conductive material for the conductive layer 12. Whereas aluminum or copper generally have been used for the conductive layer 12 (FIG. 2), titanium, titanium nitride or tungsten may be used in a conductive layer 112 of a conductive connection 114 (FIG. 3) of a semiconductor device 100. While the use of such materials tends to pinch off the size of an air gap 126 formed in an offset opening 125, in instances where the offset is relatively large, the conductive layer 112 still may not be formed as desired, thus creating the problems noted above. Further, titanium, titanium nitride and tungsten all have a higher electrical resistance than aluminum and copper within the ultimately formed conductive connection, which may create other problems.
There thus exists a need for a fabricated semiconductor device which does not tend to form the offset gap shown in FIG. 2.